Title :
An enhanced template matching algorithm and its chip implementation
Author :
Seo, Seungwan ; Sunwoo, Myung H.
Author_Institution :
Ajou Univ., Suwon, South Korea
Abstract :
This paper presents an enhanced template matching algorithm and its chip implementation. The proposed algorithm called the enhanced moment preserving pattern matching (EMPPM) improves the noise margin by 22% compared with the previously proposed algorithm called the moment preserving pattern matching (MPPM) algorithm. In addition, the proposed architecture can reduce the gate count by more than 28% compared with the MPPM architecture. We have implemented behavior and structure models using VHDL and performed logic synthesis using the SynopsysTM CAD tool. The actual chip has been implemented using the SamsungTM 0.6 μm SOG (sea-of-gate) cell library. The implemented chip consists of 35,827 gates, operates at 100 MHz and performs 16×16 template matching with a speed of 200 Mpixels/s
Keywords :
digital signal processing chips; hardware description languages; high level synthesis; image matching; logic arrays; 0.6 mum; 100 MHz; Samsung SOG cell library; Synopsys CAD tool; VHDL; architecture; behavior models; chip implementation; enhanced moment preserving pattern matching; enhanced template matching algorithm; gate count; logic synthesis; sea-of-gate cell library; structure models; Costs; Hardware; Image processing; Image registration; Libraries; Logic design; Noise robustness; Pattern matching; Performance evaluation; Quantization;
Conference_Titel :
Signal Processing Systems, 1998. SIPS 98. 1998 IEEE Workshop on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-7803-4997-0
DOI :
10.1109/SIPS.1998.715779
