• DocumentCode
    3145958
  • Title

    On Fault Detection in CMOS Logic Networks

  • Author

    Chiang, Kuang-wei ; Vranesic, Zvonko G.

  • Author_Institution
    Department of Electrical Engineering University of Ottawa
  • fYear
    1983
  • fDate
    27-29 June 1983
  • Firstpage
    50
  • Lastpage
    56
  • Abstract
    This paper considers the problem of detecting faults in CMOS combinational networks. Effects of open and short faults in CMOS networks are analyzed. It is shown that the test sequence must be properly organized if the effects of all open faults are to be observable at the network output terminal. A simple and efficient heuristic method for organizing the test sequence to detect all single faults in a CMOS network is suggested.
  • Keywords
    CMOS Circuits; Fault Detection; Test Generation; CMOS logic circuits; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Intelligent networks; Logic circuits; Logic gates; Logic testing; MOS devices; CMOS Circuits; Fault Detection; Test Generation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 1983. 20th Conference on
  • ISSN
    0738-100X
  • Print_ISBN
    0-8186-0026-8
  • Type

    conf

  • DOI
    10.1109/DAC.1983.1585625
  • Filename
    1585625
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3145958