Tools for rapid construction of VHDL performance models for DSP systems

Author

Gray, F. Gail ; Frank, Geoffrey A. ; Ziegenbein, Dirk ; Vuppala, Srilekha ; Balasubramanian, Priya

Author_Institution

Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA

fYear

1998

fDate

16-19 Mar 1998

Firstpage

77

Lastpage

82

Abstract

This paper describes a set of tools that were jointly developed by RTI and Virginia Tech that semi-automates the process of constructing VHDL performance models for DSP applications. Use of these tools allows rapid evaluation of larger design spaces than was previously feasible. This paper describes an architecture tradeoff environment that integrates our tools with several commercial tools

Keywords

digital signal processing chips; hardware description languages; logic CAD; multiprocessor interconnection networks; software prototyping; software tools; DSP systems; VHDL performance models; architecture tradeoff environment; design spaces; rapid construction; Algorithm design and analysis; Computer architecture; Computer networks; Digital signal processing; Identity-based encryption; Partitioning algorithms; Prototypes; Signal processing algorithms; Space technology; Statistics;

fLanguage

English

Publisher

ieee

Conference_Titel

Verilog HDL Conference and VHDL International Users Forum, 1998. IVC/VIUF. Proceedings., 1998 International

Conference_Location

Santa Clara, CA

ISSN

1085-9403

Print_ISBN

0-8186-8415-1

Type

conf

DOI

10.1109/IVC.1998.660684

Filename

660684