A mixed-language simulator for concurrent engineering

We have constructed a simulator that can be used to verify models of hardware whose descriptions can take a variety of forms. This simulator provides a means for sharing models among different project teams at different stages of progress. A key feature of the simulation environment is the ability to use the same test source code for stimulating C-language models, Verilog HDL RTL and gate-level models, emulation hardware, and actual hardware. The simulator can be configured so that mixtures of these model forms can be used for total system-level simulation and regression testing. Another feature of the simulator is that its implementation is fairly project-independent, having been designed to be leveraged across multiple product development cycles