Stress-balance Flip-Flops for NBTI tolerant circuit based on Fine-Grain Redundancy

Moore´s law keeps shrinking the transistor size, and timing degradation of the small transistors are becoming critical. Negative Bias Temperature Instability (NBTI) is one of the dominant cause degradation and increasing the path delay, resulting in timing errors. This paper introduces altered Fine-Grain Redundant (FGR) logic and Stress-balance Flip-Flops (SBFFs). FGR logic uses one of the two identical logic paths alternately so that one of the path recovers NBTI stress while the other path works. The SBFF prevents any transistor from keeping stressed so as to have a long life. The SBFF has more than twice as long life time than a normal FF. Therefore, FGR and SBFFs improve the reliability of the LSI circuit.