• DocumentCode
    3146182
  • Title

    A strategy for C-based verification

  • Author

    Herman, Phil

  • Author_Institution
    Mint Technol. Inc., Billerica, MA, USA
  • fYear
    1998
  • fDate
    16-19 Mar 1998
  • Firstpage
    120
  • Lastpage
    127
  • Abstract
    This paper describes a simple set of tools and techniques that can be used to develop test and verification software in the C environment and interface these tests to a Verilog/VHDL simulation. Particular attention is given to a `virtual processor´ interface between the C-based test code and the simulation engine
  • Keywords
    C language; formal verification; hardware description languages; logic CAD; C environment; C-based test code; C-based verification; Verilog/VHDL simulation; simulation engine; verification software; virtual processor; Discrete event simulation; Engines; Hardware design languages; Interactive systems; Internet; Registers; Sockets; Software testing; Video recording; Web sites;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Verilog HDL Conference and VHDL International Users Forum, 1998. IVC/VIUF. Proceedings., 1998 International
  • Conference_Location
    Santa Clara, CA
  • ISSN
    1085-9403
  • Print_ISBN
    0-8186-8415-1
  • Type

    conf

  • DOI
    10.1109/IVC.1998.660690
  • Filename
    660690
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3146182