• DocumentCode
    3146183
  • Title

    Graph-Optimization Techniques for IC Layout and Compaction

  • Author

    Kedem, Gershon ; Watanabe, Hiroyuki

  • Author_Institution
    Computer Science Department, University of Rochester, Rochester, NY
  • fYear
    1983
  • fDate
    27-29 June 1983
  • Firstpage
    113
  • Lastpage
    120
  • Abstract
    This paper describes a new approach for IC layout and compaction. The compaction problem is translated into a mixed integer-linear programming problem of a very special form. A graph based optimization algorithm is used to solve the resulting problem. An experimental program that uses the above techniques is described. The program could be used either as an aid to hand layout or as the bottom part of an automatic layout generation program.
  • Keywords
    Application specific integrated circuits; Compaction; Computer science; Digital circuits; Integrated circuit layout; Libraries; Logic circuits; Logic design; Minimization; Shape;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 1983. 20th Conference on
  • ISSN
    0738-100X
  • Print_ISBN
    0-8186-0026-8
  • Type

    conf

  • DOI
    10.1109/DAC.1983.1585635
  • Filename
    1585635
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3146183