Title :
Graph-Optimization Techniques for IC Layout and Compaction
Author :
Kedem, Gershon ; Watanabe, Hiroyuki
Author_Institution :
Computer Science Department, University of Rochester, Rochester, NY
Abstract :
This paper describes a new approach for IC layout and compaction. The compaction problem is translated into a mixed integer-linear programming problem of a very special form. A graph based optimization algorithm is used to solve the resulting problem. An experimental program that uses the above techniques is described. The program could be used either as an aid to hand layout or as the bottom part of an automatic layout generation program.
Keywords :
Application specific integrated circuits; Compaction; Computer science; Digital circuits; Integrated circuit layout; Libraries; Logic circuits; Logic design; Minimization; Shape;
Conference_Titel :
Design Automation, 1983. 20th Conference on
Print_ISBN :
0-8186-0026-8
DOI :
10.1109/DAC.1983.1585635
