Title :
HAL; A Block Level Hardware Logic Simulator
Author :
Sasaki, Tohru ; Koike, Nobuhiko ; Ohmori, Kenji ; Tomita, Kyoji
Author_Institution :
NEC Corporation, Tokyo, Japan
Abstract :
A special purpose hardware machine, which simulates up to one half million gates and 2M byte RAM ICs at a 5 millisecond clock speed, is described. This is accomplished with a HArdware Logic (HAL) simulator. This performance is achieved with 32 distributed special parallel processors, which utilize Block Oriented Simulation Technique. The technique promises a good cost hardware logic simulator.
Keywords :
Clocks; Computational modeling; Computer simulation; Hardware; Large scale integration; Logic arrays; Logic design; Process control; Random access memory; Read-write memory;
Conference_Titel :
Design Automation, 1983. 20th Conference on
Print_ISBN :
0-8186-0026-8
DOI :
10.1109/DAC.1983.1585641