A loosely coupled C/Verilog environment for system level verification

TestBenchPlus is a high-level system verification software tool and methodology which focuses on using diagnostic code and application software together with specialized verification code to provide a verification environment which carries through from subsystem testing to a fully integrated system-level verification test. The major goals of TestBenchPlus are to exercise the system in a manner similar to how it will actually be used, to minimize throwaway verification code, and to provide an environment which fosters reuse of verification and diagnostic code within a project as the level of integration increases, and between projects that have some level of architectural similarity. In this paper, we present some of the basic concepts of this method, and results from a variety of projects in which we have successfully utilized this approach