Optimized poly-Si/sub 1-x/Ge/sub x/-gate technology for dual gate CMOS application

Scaling of CMOS technology to the deep-submicron regime has been driven by the need for higher speed and integration density, as well as lower power operation. Dual-gate technology offers several advantages, including reduced short-channel effect (SCE) by surface-channel operation of both NMOS and PMOS devices, and low and symmetrical threshold voltages required for low supply voltages. However, new problems such as the poly-gate-depletion effect (PDE) emerge as the dimensions of devices enter the deep-submicron regime. Poly-Si/sub 1-x/Ge/sub x/ has recently been reported as a promising alternative gate material. Poly-Si/sub 1-x/Ge/sub x/-gated devices with lower gate sheet resistance, higher current drive and less PDE as compared to conventional poly-Si-gated devices have been demonstrated. In this work poly-Si/sub 1-x/Ge/sub x/ dual-gate CMOS performance is demonstrated to be optimized at /spl sim/20% Ge content in terms of SCE and PDE. The use of poly-Si/sub 1-x/Ge/sub x/ gate can help to alleviate boron penetration problem without degrading gate oxide reliability.