• DocumentCode
    3146389
  • Title

    Evaluating In-Clique and Topological Parallelism Strategies for Junction Tree-Based Bayesian Network Inference Algorithm on the Cray XMT

  • Author

    Chin, George ; Choudhury, Sutanay ; Kangas, Lars ; McFarlane, Sally ; Marquez, Andres

  • Author_Institution
    Pacific Northwest Nat. Lab., Richland, WA, USA
  • fYear
    2011
  • fDate
    16-20 May 2011
  • Firstpage
    1710
  • Lastpage
    1719
  • Abstract
    Long viewed as a strong statistical inference technique, Bayesian networks have emerged as an important class of applications for high-performance computing. We have applied an architecture-conscious approach to parallelizing the Lauritzen-Spiegelhalter Junction Tree algorithm for exact inferencing of Bayesian networks. In optimizing the Junction Tree algorithm, we have implemented both in-clique and topological parallelism strategies to best leverage the fine-grained synchronization and massive-scale multithreading of the Cray XMT architecture. Two topological techniques were developed to parallelize the evidence propagation process through the Bayesian network. The first technique involves performing intelligent scheduling of junction tree nodes based on the tree´s topology and the relative sizes of nodes. The second technique involves decomposing the junction tree into a finer state graph representation to offer many more opportunities for parallelism. We evaluate these optimizations on five different Bayesian networks and report our findings and observations. From this development and evaluation, we demonstrate the application of massive-scale multithreading for load balancing and use of implicit parallelism-based compiler optimizations for designing scalable inferencing algorithms.
  • Keywords
    belief networks; graphs; inference mechanisms; multi-threading; statistical analysis; synchronisation; trees (mathematics); Cray XMT architecture; Lauritzen-Spiegelhalter junction tree algorithm; architecture conscious approach; in-clique parallelism; intelligent scheduling; junction tree-based Bayesian network inference algorithm; load balancing; massive scale multithreading; parallelism-based compiler optimization; state graph representation; statistical inference technique; topological parallelism strategy; Algorithm design and analysis; Bayesian methods; Inference algorithms; Instruction sets; Junctions; Parallel processing; Particle separators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW), 2011 IEEE International Symposium on
  • Conference_Location
    Shanghai
  • ISSN
    1530-2075
  • Print_ISBN
    978-1-61284-425-1
  • Electronic_ISBN
    1530-2075
  • Type

    conf

  • DOI
    10.1109/IPDPS.2011.328
  • Filename
    6009037