A study about FPGA-based digital filters

Author

Valls, Javier ; Peiro, Marcos M. ; Sansaloni, Trini ; Boemo, Eduardo

Author_Institution

Univ. Politecnica de Valencia, Spain

fYear

1998

fDate

8-10 Oct 1998

Firstpage

192

Lastpage

201

Abstract

A set of operators suitable for digit-serial FIR filtering is presented. The canonical and inverted forms are studied. In each of these structures both the symmetrical and anti-symmetrical particular cases are also covered. All circuits have been implemented using an EPF10K50 Altera FPGA. The main results show that the canonical form presents less occupation and higher throughput. The 8-tap filter versions implemented can be applied in real-time processing with sample rate ranging up to 7 MHz using the bit-serial versions and up to 25 MHz with the bit-parallel ones

Keywords

FIR filters; digital signal processing chips; field programmable gate arrays; real-time systems; signal sampling; 8-tap filter versions; EPF10K50 Altera FPGA; bit-parallel versions; bit-serial versions; canonical forms; digit-serial FIR filtering; digital filters; inverted forms; operators; real-time processing; sample rate; Arithmetic; Circuits; Computer architecture; Costs; Digital filters; Digital signal processing; Field programmable gate arrays; Filtering; Finite impulse response filter; Integrated circuit interconnections; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems, 1998. SIPS 98. 1998 IEEE Workshop on

Conference_Location

Cambridge, MA

ISSN

1520-6130

Print_ISBN

0-7803-4997-0

Type

conf

DOI

10.1109/SIPS.1998.715782

Filename

715782