A Coverage-Driven Constraint Random-Based Functional Verification Method of Pipeline Unit

This paper presents a coverage-driven constraint random-based functional verification (CCRFV) method of pipeline unit in a microprocessor. The environment of verification, which is created by means of verification methodology manual (VMM) for SystemVerilog, is reusable and can reduce verification time. The model created by combining classification trees, which can ensure to cover complete coverage and to close the gap from the specification of a test plan to SystemVerilog. Using this environment of verification, we can not only know whether there are bugs in the design under test (DUT) or not, but also can easily locate design errors.