Title :
SAVANT/TyVIS/WARPED: components for the analysis and simulation of VHDL
Author :
Wilsey, Philip A. ; Martin, Dale E. ; Subramani, Krishnan
Author_Institution :
Dept. of ECECS, Cincinnati Univ., OH, USA
Abstract :
The SAVANT, QUEST II, and HEPE research programs at the University of Cincinnati include the development and distribution of VHDL analysis and simulation capabilities. These capabilities are being freely distributed for non-commercial use. The SAVANT project is underway specifically to develop a VHDL analyzer with a well-documented, extensible intermediate form; the main objective is to smooth the integration of VHDL technology into university and industrial research programs. The SAVANT project is funded through the Air Force SBIR program and is a joint activity between the University of Cincinnati and MTL Systems, Inc. The QUEST II program is investigating parallel algorithms and architectures for simulation, behavioral synthesis, and ATPG. The HEPE program is investigating (in part) novel strategies for relaxing causal orders in the parallel simulation of active networks. As part of the QUEST II/HEPE simulation activities, a VHDL simulation kernel is being developed that will operate with the SAVANT intermediate form for sequential or parallel execution of VHDL models (a C++ code generator from the SAVANT intermediate is being jointly developed by the SAVANT and QUEST II programs). All of the software from the QUEST and HEPE simulation programs is freely available for use (commercial or otherwise)
Keywords :
hardware description languages; parallel algorithms; parallel architectures; parallel programming; system monitoring; virtual machines; ATPG; Air Force SBIR program; HEPE research program; QUEST II research program; SAVANT research program; TyVIS; VHDL analyzer; VHDL simulation kernel; WARPED; active networks; behavioral synthesis; parallel algorithms; parallel architectures; parallel execution; parallel simulation; sequential execution; software; Analytical models; Automatic test pattern generation; Computational modeling; Computer architecture; Contracts; Discrete event simulation; Electrical capacitance tomography; Kernel; Laboratories; Read only memory;
Conference_Titel :
Verilog HDL Conference and VHDL International Users Forum, 1998. IVC/VIUF. Proceedings., 1998 International
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-8186-8415-1
DOI :
10.1109/IVC.1998.660701