Title :
Design for Test Calculus: An Algorithm for DFT Rules Checking
Author :
Bhavsar, Dilip K.
Author_Institution :
General Electric Company Electronics Laboratory, Syracuse, NY
Abstract :
A new one-pass algorithm for checking networks for compliance to a set of Design for Test (DFT) rules is presented. The algorithm is based on a "Design For Test Calculus" which defines various types of signals and nodes in the network, signal sets attached to node\´s inputs and outputs, and rules for transferring signal sets through nodes. The rule checking is accomplished by examining the characteristic contents of the signal sets transferred. The calculus is capable of handling a wide variety of "test point flip-flops" and test access schemes, and has features that make hierarchical rule checking feasible.
Keywords :
Algorithm design and analysis; Calculus; Circuit testing; Design for testability; Electronic equipment testing; Flip-flops; Logic design; Logic testing; System testing; Very large scale integration;
Conference_Titel :
Design Automation, 1983. 20th Conference on
Print_ISBN :
0-8186-0026-8
DOI :
10.1109/DAC.1983.1585666