DocumentCode :
3146922
Title :
Symbolic Parasitic Extractor for Circuit Simulation (SPECS)
Author :
Bastian, J.D. ; Ellement, M. ; Fowler, P.J. ; Huang, C.E. ; McNamee, L.P.
Author_Institution :
Rockwell International Corporation, Defense Electronics Operations Microelectronics Research & Development, Anaheim, CA
fYear :
1983
fDate :
27-29 June 1983
Firstpage :
346
Lastpage :
352
Abstract :
This paper describes the design, development and implementation of the program SPECS. The purpose of SPECS is to automatically extract from a Rockwell microelectronic symbolic matrix description a netlist for circuit simulation. This program differs from others in that it uses a symbol layout matrix as an input, calculates both interelectrode and intrinsic capacitance, calculates conductor resistance, produces a schematic representation of the network and has a selective TRACE, i.e., traces only the circuit or network of interest.
Keywords :
Circuit simulation; Computational modeling; Computer science; Computer simulation; Conductors; Design automation; Integrated circuit interconnections; Microelectronics; Parasitic capacitance; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1983. 20th Conference on
ISSN :
0738-100X
Print_ISBN :
0-8186-0026-8
Type :
conf
DOI :
10.1109/DAC.1983.1585672
Filename :
1585672
Link To Document :
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