A Layout Verification System for Analog Bipolar Integrated Circuits

A new layout verification system, called ALAS (A Layout Analysis System) is presented. Its main intention is to tackle the particular verification problems of analog bipolar circuits. At present, the system comprises four main parts: a device recognition program produces a list of devices, a plot program converts these data to a layout-oriented circuit diagram, a connectivity analysis program yields device-oriented or net-oriented descriptions of the derived circuit and a network comparison program tests the consistency of this actual circuit with the intended nominal one. A fifth program, that will calculate the parameters of the actual circuit, is under development. To derive the actual circuit from layout ALAS uses geometrical mask data only; no additional circuit information is needed. If not available from the design system, a description of the nominal circuit may be supplied manually in a SPICE-like input format.