Efficient program control schemes for Motion Estimation specific processor

This paper proposes two program control schemes for a Motion Estimation (ME) Application Specific Instruction-set Processor (ASIP). The proposed dynamic pipeline control scheme can reduce the pipeline stall caused by H/W accelerators. In addition, three loop instructions and their specific architecture are also proposed to support efficient H/W loop operations. The simulation results show that the dynamic pipeline control scheme can save 9.03% computation times and the proposed hardware loop scheme can reduce about 29.26% average instruction cycles compared with existing loop instructions. Due to the improvement of processor efficiency and the reduction of program memory accesses, the proposed program control schemes for ME ASIP are quite suitable for low power and high performance ME implementation.