• DocumentCode
    3147092
  • Title

    I-NET mechanism for issuing multiple instructions

  • Author

    Wang, Lingtao ; Wu, Chuan-lin

  • Author_Institution
    Motorola Inc., Austin, TX, USA
  • fYear
    1988
  • fDate
    14-18 Nov 1988
  • Firstpage
    88
  • Lastpage
    95
  • Abstract
    Conventional instruction issuing methods use hardware control mechanism to issue instructions in multiple-functional-unit systems. They reach physical limitations due to the complexity of issuing logic when they intend to issue multiple instruction per cycle. A method called I-NET is proposed to overcome this shortcoming. I-NET uses a postcompiler to detect the data dependencies among instructions. The detected data dependence is then attached to the instruction code to form an instruction unit that can be executed independently with other such units. These precoded instruction units are fetched from the memory and sent to functional units directly. A maximal instruction-issuing rate is achieved by avoiding a lengthy decoding procedure in the hardware. The performance study has shown I-NET to be a very promising method for exploring massive parallelism of a program in a multiple-functional-unit system
  • Keywords
    parallel processing; I-NET; data dependencies; detect; functional units; instruction code; massive parallelism; maximal instruction-issuing rate; memory; multiple instructions; multiple-functional-unit systems; performance; postcompiler; precoded instruction units; Computer buffers; Control systems; Decoding; Hardware; Logic; Multiprocessor interconnection networks; Parallel processing; Routing; Signal detection; Sorting;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Supercomputing '88. [Vol.1]., Proceedings.
  • Conference_Location
    Orlando, FL
  • Print_ISBN
    0-8186-0882-X
  • Type

    conf

  • DOI
    10.1109/SUPERC.1988.44641
  • Filename
    44641