DocumentCode :
3147369
Title :
A Codesigned Fault Tolerance System for Heterogeneous Many-Core Processors
Author :
Yim, Keun Soo ; Iyer, Ravishankar K.
Author_Institution :
Coordinated Sci. Lab., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
fYear :
2011
fDate :
16-20 May 2011
Firstpage :
2053
Lastpage :
2056
Abstract :
This paper presents an efficient fault tolerance system for heterogeneous many-core processors. The efficiencies and coverage of the presented fault tolerance are optimized by customizing the techniques for different types of components in the highest layers of system abstractions and codesigning the techniques in a way that separates algorithms and mechanisms.
Keywords :
fault tolerant computing; multiprocessing systems; codesigned fault tolerance system; heterogeneous many-core processors; system abstraction; Cloning; Detectors; Fault tolerance; Fault tolerant systems; Hardware; Program processors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW), 2011 IEEE International Symposium on
Conference_Location :
Shanghai
ISSN :
1530-2075
Print_ISBN :
978-1-61284-425-1
Electronic_ISBN :
1530-2075
Type :
conf
DOI :
10.1109/IPDPS.2011.375
Filename :
6009088
Link To Document :
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