A power grid optimization algorithm considering timing degradation by NBTI

Reliability becomes one of the most important issues for designing LSIs. Negative bias temperature instability (NBTI) is a phenomenon in which the performance of a transistor deteriorates depending on the temperature and the transistor switching frequency. In the manufacturing process generations of 32 nm and 22 nm, it will be expected that timing degradation by NBTI becomes non-ignorable. This paper proposes a high reliable power grid optimization technique in which timing degradation by NTBI of after-manufacture five or ten years is taken into consideration.