Word-length optimization of a pipelined FFT processor

In this paper, word-length optimization for a pipelined 8K FFT processor is presented. The processor is based on radix-2/4/8 and mixed radix algorithm, and SDF architecture is used. The internal word-length and data format are important issues when designing pipelined FFT processors, it will affect precision and gate number. To obtain a good solution, three Matlab models for the processor are developed in which the internal data are formatted as floating point, fixed point and hybrid floating point respectively, and simulations are performed. The simulation results show that hybrid floating point can achieve better and constant performance compared to fixed point with progressive word-length in term of SQNR and memory size.