Computer-Aided Partitioning of Behavioral Hardware Descriptions

This paper describes an algorithm for partitioning a behavioral hardware description written in the ISPS computer hardware description language. The partitioning is done before the actual registers, processing elements, and interconnections have been chosen, so that the partitioning information can be used to guide the design of the data path structure. An experiment was conducted in which a partition produced by the algorithm was compared to partitions done by human designers. The automatic partition was found to be in close agreement with those done by the designers.