A host-accelerator communication architecture design for efficient binary acceleration

Binary acceleration of a kernel on an accelerator may have a data duplication problem. Some data in an address range may be copied into the local memory of the accelerator incurring data copy overhead as well as a coherence problem. Configurable Range Memory (CRM) is a memory shared by the host processor and the accelerator, which can specify its own address range such that the data within the range can be directly loaded into it. However, the memory may need to be carefully designed considering the memory access patterns of the accelerator not to incur any unnecessary overhead. This work presents a new CRM architecture and shows how it improves the system performance with a novel Coarse-Grained Reconfigurable Array (CGRA) architecture.