Functional Simulation Shortens the Development Cycle of a New Computer

A high-performance VLSI CPU subsystem for an Ada-oriented 32-bit Instruction Set Architecture was effectively designed and validated on a short schedule using the ISP´ hardware descriptive language and N.mPc functional simulation tools. The architecture employs a horizontal microcode structure that drives numerous parallel hardware functions to achieve a throughput performance approaching 3 mips. The design approach incorporated construction of individual ISP´ models and simulation of the total system to ensure the functional correctness of the total architecture, the VLSI device partitions, and the detailed interfaces. Additionally, firmware for the complete instruction set was produced and verified by means of simulation on the models. The effectiveness of this approach is evidenced by the efficient CPU functional design and validation work and the rapid integration of the microcode on an advanced development model of the system. The success of this design approach has been a key factor in meeting the development schedule.