• DocumentCode
    3147699
  • Title

    A Framework for Automated Performance Tuning and Code Verification on GPU Computing Platforms

  • Author

    Gehrke, Allison S. ; Ra, Ilkyeun ; Connors, Daniel A.

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Univ. of Colorado Denver, Denver, CO, USA
  • fYear
    2011
  • fDate
    16-20 May 2011
  • Firstpage
    2113
  • Lastpage
    2116
  • Abstract
    Emerging multi-core processor designs create a computing paradigm capable of advancing numerous scientific areas, including medicine, data mining, biology, physics, and earth sciences. However, the trends in multi-core hardware technology have advanced far ahead of the advances in software technology and programmer productivity. For the most part, current scientists only leverage multi-core and GPU (Graphical Processing Unit) computing platforms after painstakingly uncovering the inherent task and data-level parallelism in their application. In many cases, the development does not realize the full potential of the parallel hardware. There exists an opportunity to meet the challenges in optimally mapping scientific application domains to multi-core computer systems through the use of compile-time and link-time optimization strategies. We are exploring a code compilation framework that automatically generates and tunes numerical solver codes for optimal performance on graphical processing units. The framework advances computational simulation in kinetic modeling by significantly reducing the execution time of scientific simulations and enabling scientists to compare results to previous models and to extend, modify, and test new models without code changes.
  • Keywords
    computer graphic equipment; coprocessors; multiprocessing systems; optimisation; performance evaluation; program compilers; GPU computing platforms; automated performance tuning; code compilation framework; code verification; compile time; data level parallelism; kinetic modeling; link time optimization strategies; multicore processor designs; parallel hardware; Computational modeling; Data models; Graphics processing unit; Kinetic theory; Numerical models; Optimization; Registers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW), 2011 IEEE International Symposium on
  • Conference_Location
    Shanghai
  • ISSN
    1530-2075
  • Print_ISBN
    978-1-61284-425-1
  • Electronic_ISBN
    1530-2075
  • Type

    conf

  • DOI
    10.1109/IPDPS.2011.390
  • Filename
    6009101