Design Space Exploration for Power-Efficient Mixed-Radix Ling Adders

We present an integer linear programming (ILP) method that optimizes generalized prefix Ling adders in terms of area, delay, and power. The contribution is listed in the following. (1) We devise an ILP formulation based on logical effort models so that we can use ILP solver, CPLEX, to produce minimum power solutions with given structural, area and timing constraints. The formulation allows the adjustment of parameters and constraints, e.g. the radix numbers and the ratio of static and dynamic power. We implement the flow for the users to automatically synthesize the adders. (2) We engineer sets of integer decision variables and linear constraints to depict the prefix topology, signal delay, and power characterization. Since the design space of prefix adders is large, optimal solutions are usually hard to generate without good formulations. We generate redundant constraints to prune the search space. The approach significantly reduces the execution time. (3) We explore mixed radices for prefix topologies, i.e. GP cells have radices 2, 3, or 4, and a prefix network can contain cells of different radices. This mixed-radix feature expands the design space for better solutions. High-radix adders reduce logic levels and thus can serve for high performance applications. On the other hand, high-radix cells take more logical effort, longer parasitic delay, and more power consumption. These factors are all taken care of in the devised ILP formulation. (4) We adopt the structure of Ling adders to produce faster sum and carry responses. The experiments show that Ling adders achieve better results than normal prefix adders. (5) We apply hierarchical design methods to handle high bit-width modules. One weakness of ILP solver is the scaleability of computational time with the bit-width. We use a divide-and-conquer strategy to synthesize 64-bit adders.