DocumentCode :
3147876
Title :
iWarp: an integrated solution to high-speed parallel computing
Author :
Borkar, Shekhar ; Cohn, Robert ; Cox, George ; Gleason, Sha ; Gross, Thomas ; Kung, H.T. ; Lam, Monica ; Moore, Brian ; Peterson, Craig ; Pieper, John ; Rankin, Linda ; Tseng, P.S. ; Sutton, Jim ; Urbanski, John ; Webb, Jon
Author_Institution :
Intel Corp., Hillsboro, OR, USA
fYear :
1988
fDate :
14-18 Nov 1988
Firstpage :
330
Lastpage :
339
Abstract :
A description is given of the iWarp architecture and how it supports various communication models and system configurations. The heart of an iWarp system is the iWarp component: a single-chip processor that requires only the addition of memory chips to form a complete system building block, called the iWarp cell. Each iWarp component contains both a powerful computation engine that runs at 20 MFLOPS (million floating-point operations per second) and a high-throughput (320 Mb/s), low-latency (100-150-ns) communication engine for interfacing with other iWarp cells. Because of their strong computation and communication capabilities, the iWarp components provide a versatile building block for high-performance parallel systems ranging from special-purpose systolic arrays to general-purpose distributed memory computers. They can support both fine-grain parallel and coarse-grain distributed computation models simultaneously in the same system. The initial iWarp demonstration system consists of an 8×8 torus of iWarp cells, delivering more than 1.2 GFLOP (billions of FLOPS). It can be expanded to include up to 1024 cells
Keywords :
parallel architectures; 20 MFLOPS; coarse-grain distributed computation models; communication models; fine-grain parallel; general-purpose distributed memory computers; high-speed parallel computing; iWarp architecture; integrated solution; memory chips; single-chip processor; special-purpose systolic arrays; system configurations; Computational modeling; Computer architecture; Computer interfaces; Concurrent computing; Distributed computing; Engines; Heart; Parallel processing; Power system modeling; Systolic arrays;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Supercomputing '88. [Vol.1]., Proceedings.
Conference_Location :
Orlando, FL
Print_ISBN :
0-8186-0882-X
Type :
conf
DOI :
10.1109/SUPERC.1988.44670
Filename :
44670
Link To Document :
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