DocumentCode
3147909
Title
Impact of ground line position on CMOS interconnect behavior
Author
Ktata, M. Faiez ; Arz, Uwe ; Grabinski, Hartmut ; Fischer, Helmut
Author_Institution
Memory Products Div., Infineon Technol., Munich, Germany
fYear
2004
fDate
2-3 Dec. 2004
Firstpage
207
Lastpage
211
Abstract
We investigate the impact of ground line position as well as the effects of conductive substrates with different conductivities of 10 S/m (low), 100 S/m (medium) and 10.000 S/m (high) on on-chip interconnects. Characteristic line parameters obtained from field calculations are validated with two-port network analyzer measurements of specially designed test structures in a frequency range up to 50 GHz.
Keywords
CMOS integrated circuits; electrical conductivity; integrated circuit interconnections; substrates; 0 to 50 GHz; 10 to 10.000 S/m; CMOS interconnect behavior; characteristic line parameters; ground line position; on-chip interconnects; substrate conductivity; two-port network analyzer measurements; Aluminum; CMOS technology; Conducting materials; Conductivity measurement; Frequency measurement; Manufacturing; Network-on-a-chip; Planarization; Position measurement; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Microwave Measurements Conference, Fall 2004. 64th ARFTG
Print_ISBN
0-7803-8952-2
Type
conf
DOI
10.1109/ARFTGF.2004.1427600
Filename
1427600
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