DocumentCode :
3147964
Title :
Automatic Routing of Double Layer Gate Arrays Using a Moving Cursor
Author :
Prazic, B.D. ; Bozier, M.A.
Author_Institution :
GEC Research Laboratories, Hirst Research Centre, Wembley, UK
fYear :
1983
fDate :
27-29 June 1983
Firstpage :
644
Lastpage :
650
Abstract :
This paper presents an efficient algorithm for routing of the interconnections on a large gate array layout. The algorithm employs a vertical cursor strip that traverses the chip in a single pass, laying horizontal segments in its wake on one layer, and vertical segments within the cursor itself, generally on the other layer. The routing algorithm presented here was developed as part of the UK5000 design automation system for large gate arrays and was written in standard FORTRAN 77. Routing results are presented for two gate array layouts.
Keywords :
Algorithm design and analysis; CMOS technology; Design automation; Integrated circuit interconnections; Laboratories; Large scale integration; Logic arrays; Partitioning algorithms; Routing; Standards development;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1983. 20th Conference on
ISSN :
0738-100X
Print_ISBN :
0-8186-0026-8
Type :
conf
DOI :
10.1109/DAC.1983.1585723
Filename :
1585723
Link To Document :
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