An efficient pipelined dataflow processor architecture

It is demonstrated that the principles of pipelined instruction execution can be effectively applied in data-flow computers, yielding an architecture that avoids the main sources of pipeline gaps during program execution in many conventional designs. The processing element uses an architecture called argument-fetch data-flow architecture. It has two parts: a data-flow instruction scheduling unit (DISU) and a pipelined instruction processing unit (PIPU). The PIPU is an instruction processor that uses many conventional techniques to achieve fast pipelined operation. The DISU holds the data-flow signal graph of the collection of data-flow instructions allocated to the processing element and maintains a large pool of enabled instructions available for execution by the PIPU. The architecture provides a basis for achieving high performance for many scientific applications. The trial design and fabrication of an enable memory, a key component of the DISU, are reported