Title :
Datapath Synthesis for Standard-Cell Design
Author :
Zimmermann, Reto
Author_Institution :
Solutions Group, Synopsys Switzerland LLC, Zurich, Switzerland
Abstract :
Datapath synthesis for standard-cell design goes through extraction of arithmetic operations from RTL code, high-level arithmetic optimizations and netlist generation. Numerous architectures and optimization strategies exist that result in circuit implementations with very different performance characteristics. This work summarizes the circuit architectures and techniques used in a commercial synthesis tool to optimize cell-based datapath netlists for timing, area and power.
Keywords :
digital arithmetic; logic design; RTL code; arithmetic operation; circuit architecture; datapath synthesis; high-level arithmetic optimization; netlist generation; standard-cell design; Circuit synthesis; Constraint optimization; Delay; Design optimization; Digital arithmetic; Encoding; Libraries; Multiplexing; Time factors; Timing; adder; arithmetic; datapath; low-power; multiplier; standard-cell; synthesis;
Conference_Titel :
Computer Arithmetic, 2009. ARITH 2009. 19th IEEE Symposium on
Conference_Location :
Portland, OR
Print_ISBN :
978-0-7695-3670-5
DOI :
10.1109/ARITH.2009.28
