DocumentCode
3148037
Title
An optimized MC interpolation architecture for HEVC
Author
Guo, Zhengyan ; Zhou, Dajiang ; Goto, Satoshi
Author_Institution
Grad. Sch. of Inf., Production & Syst. LSI, Waseda Univ., Fukuoka, Japan
fYear
2012
fDate
25-30 March 2012
Firstpage
1117
Lastpage
1120
Abstract
In the latest draft video compression standard, HEVC, a new 8-tap MC interpolation filter is adopted. For this component, we propose an efficient VLSI design which is composed of a reconfigurable filter, an optimized pipeline engine organization, and a filter reuse scheme. This results in 30% area saving from a non-optimized design. The proposed implementation supports a maximal throughput of QFHD@60fps. Our results also demonstrate the implementation cost of a well optimized HEVC interpolation component can be comparable to that of H.264, despite of the enhanced coding performance.
Keywords
VLSI; data compression; filtering theory; interpolation; motion compensation; video coding; HEVC interpolation component; QFHD; VLSI design; coding performance; high efficiency video coding; motion compensation; nonoptimized design; optimized MC interpolation filter; pipeline engine organization; reconfigurable filter; video compression standard; Adders; Computer architecture; Engines; Equations; Hardware; Interpolation; Mathematical model; HEVC; interpolation; motion compensation;
fLanguage
English
Publisher
ieee
Conference_Titel
Acoustics, Speech and Signal Processing (ICASSP), 2012 IEEE International Conference on
Conference_Location
Kyoto
ISSN
1520-6149
Print_ISBN
978-1-4673-0045-2
Electronic_ISBN
1520-6149
Type
conf
DOI
10.1109/ICASSP.2012.6288083
Filename
6288083
Link To Document