• DocumentCode
    3148211
  • Title

    Testing for Bridging Faults (Shorts) in CMOS Circuits

  • Author

    Acken, John M.

  • Author_Institution
    Sandia National Laboratories, Albuquerque, NM
  • fYear
    1983
  • fDate
    27-29 June 1983
  • Firstpage
    717
  • Lastpage
    718
  • Abstract
    The stuck-at fault model, which is commonly used with fault simulation, does not adequately evaluate the effects of bridging faults (shorts between adjacent signal lines) in CMOS circuits. Tests for bridging faults can be performed on automatic test equipment, and the test vectors can be evaluated using logic simulation.
  • Keywords
    Automatic logic units; Automatic test equipment; Automatic testing; CMOS logic circuits; Circuit faults; Circuit simulation; Circuit testing; Logic testing; Performance evaluation; Semiconductor device modeling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 1983. 20th Conference on
  • ISSN
    0738-100X
  • Print_ISBN
    0-8186-0026-8
  • Type

    conf

  • DOI
    10.1109/DAC.1983.1585734
  • Filename
    1585734
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3148211