Title :
Testing for Bridging Faults (Shorts) in CMOS Circuits
Author_Institution :
Sandia National Laboratories, Albuquerque, NM
Abstract :
The stuck-at fault model, which is commonly used with fault simulation, does not adequately evaluate the effects of bridging faults (shorts between adjacent signal lines) in CMOS circuits. Tests for bridging faults can be performed on automatic test equipment, and the test vectors can be evaluated using logic simulation.
Keywords :
Automatic logic units; Automatic test equipment; Automatic testing; CMOS logic circuits; Circuit faults; Circuit simulation; Circuit testing; Logic testing; Performance evaluation; Semiconductor device modeling;
Conference_Titel :
Design Automation, 1983. 20th Conference on
Print_ISBN :
0-8186-0026-8
DOI :
10.1109/DAC.1983.1585734
