ILS -- Interactive Logic Simulator

Due to increasing VLSI complexity, logic level simulators have become necessary tools for design verification and test generation. Logic simulators must respond to this increased demand by providing additional functionality in a user-friendly environment. ILS (Interactive Logic Simulator) currently under development in the CAD lab of Hewlett-Packard Co. provides these features. ILS accepts a hierarchical, scoped description of the network topology. This description may consist of libraries, blocks, ILS-defined primitives (transistors and gates), or user-defined primitives. These multiple levels simplify network description and allow ILS to accurately simulate a wide variety of circuits. The simulator incorporates a new modeling scheme which allows functional, logic, and circuit level primitives to communicate efficiently. In addition, ILS features a new concept in simulation control languages to facilitate generation of functional test programs. This paper will briefly review these significant benefits provided by the ILS simulator.