• DocumentCode
    3148310
  • Title

    A new adaptive bit synchronizer based on DDS

  • Author

    Luo, Chang ; Li, Jiye ; Chen, Xiaomin

  • Author_Institution
    Center for Space Sci. & Appl. Res., Chinese Acad. of Sci., Beijing, China
  • fYear
    2011
  • fDate
    16-18 April 2011
  • Firstpage
    2877
  • Lastpage
    2880
  • Abstract
    A new adaptive full digital bit synchronizer, which uses the structure of digital phase-locked loop comprised of lead-lag phase detector and direct digital synthesizer (DDS) is designed based on FPGA. The synchronizer has adaptive characteristic, so the modified quantities of phase can be self adjustment based on difference of the phase. It has also programmable characteristic, so frequency resolution, trace step size and phase accuracy can be set previously for the need. The analysis results show that the bit synchronizer has high phase accuracy, wide acquisition range, short latch-down time and good adaptation and timing-jitter performance. It can be implemented easily based on FPGA.
  • Keywords
    digital phase locked loops; direct digital synthesis; field programmable gate arrays; phase detectors; DDS; FPGA; adaptive full digital bit synchronizer; digital phase-locked loop; direct digital synthesizer; good adaptation; high phase accuracy; lead-lag phase detector; short latch-down time; timing-jitter performance; wide acquisition range; Accuracy; Detectors; Field programmable gate arrays; Lead; Phase locked loops; Synchronization; Synthesizers; FPGA; digital phase-locked loop; direct digital synthesizer; lead-lag phase detector; synchronizer;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Consumer Electronics, Communications and Networks (CECNet), 2011 International Conference on
  • Conference_Location
    XianNing
  • Print_ISBN
    978-1-61284-458-9
  • Type

    conf

  • DOI
    10.1109/CECNET.2011.5768234
  • Filename
    5768234