Title :
A High-Performance Significand BCD Adder with IEEE 754-2008 Decimal Rounding
Author :
Vázquez, Alvaro ; Antelo, Elisardo
Author_Institution :
Dept. of Electron. & Comput. Eng., Univ. of Santiago de Compostela, Santiago de Compostela, Spain
Abstract :
We present a new method and architecture to merge efficiently IEEE 754-2008 decimal rounding with significand BCD addition and subtraction. This is a key component to improve several decimal floating-point operations such as addition, multiplication and fused multiply-add. The decimal rounding unit is based on a direct implementation of the IEEE 754-2008 rounding modes. We show that the resultant implementations for IEEE 754-2008 Decimal64 (16 precision digits) and Decimal128 (34 precision digits) formats reduce significantly the area and latency required for significand BCD addition/subtraction and decimal rounding in previous high-performance decimal floating-point adders.
Keywords :
IEEE standards; adders; digital arithmetic; BCD addition-subtraction; Decimal128 format; IEEE 754-2008 Decimal64; IEEE 754-2008 decimal rounding; IEEE 754-2008 rounding mode; decimal floating-point operation; decimal rounding unit; high-performance decimal floating-point adder; high-performance significand BCD adder; Added delay; Adders; Computer architecture; Consumer electronics; Contracts; Delay effects; Digital arithmetic; Floating-point arithmetic; Parallel architectures; Tin;
Conference_Titel :
Computer Arithmetic, 2009. ARITH 2009. 19th IEEE Symposium on
Conference_Location :
Portland, OR
Print_ISBN :
978-0-7695-3670-5
DOI :
10.1109/ARITH.2009.30
