HOPLA - PLA Optinization and Synthesis

A system that automates Programmable Logic Array optimization and synthesis for VLSI design is described. PLA logic is defined via a high level Hardware Definition Language. After translation to table representation comes the logic optimization phase, carried out according to a user defined optimization criterion. The geometrical optimization phase follows, supplemented by a manual interactive graphic PLA editor. The system outputs symbolic Layout of the PLA which can be translated into polygon-level layout.