DocumentCode
3148842
Title
A scalable VLSI architecture for multichannel blind deconvolution and source separation
Author
Pan, H. ; Xia, D. ; Douglas, S.C. ; Smith, K.F.
Author_Institution
Dept. of Electr. Eng., Utah Univ., Salt Lake City, UT, USA
fYear
1998
fDate
8-10 Oct 1998
Firstpage
297
Lastpage
306
Abstract
In this paper, we describe a scalable VLSI architecture for a signal processing system that separates multiple independent source signals from a set of linear, convolved mixtures. The architecture employs a recently-proposed entropy-based algorithm and consists of a two dimensional array of interconnected chips, each of which implements a two-input, two-output signal separation system. With a maximum of 255 filter coefficients per input-output channel. Chip communication is realized via separate state machines within each chip to simplify the design and enable its scalability to larger tasks. An application of the architecture to speech separation is described
Keywords
VLSI; deconvolution; digital signal processing chips; entropy; finite state machines; speech processing; systolic arrays; chip communication; entropy-based algorithm; filter coefficients; input-output channel; input-output signal separation system; interconnected chips; linear convolved mixtures; multichannel blind deconvolution; multiple independent source signals; scalable VLSI architecture; signal processing system; source separation; speech separation; systolic like array; two dimensional array; Array signal processing; Cities and towns; Computer architecture; Deconvolution; Filters; Scalability; Signal processing; Signal processing algorithms; Source separation; Speech; Speech processing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing Systems, 1998. SIPS 98. 1998 IEEE Workshop on
Conference_Location
Cambridge, MA
ISSN
1520-6130
Print_ISBN
0-7803-4997-0
Type
conf
DOI
10.1109/SIPS.1998.715792
Filename
715792
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