Workload-balancing schedule with adaptive architecture of MPSoCs for fault tolerance

With the scaling of semiconductor technology, the reliability of embedded multiprocessor systems has become one of the major concerns of the industry. Meanwhile, the communication cost of processors on a chip is becoming a hot topic both in research and in product development. However, most list scheduling heuristics rely on the assumption that processors in the systems are completely safe. To schedule precedence graphs in a more realistic framework, we propose a bus-based adaptive architecture and introduce a workload-balancing schedule algorithm for fault tolerance in this paper. The proposed techniques are capable of balancing the load among processors, supporting one processor failure and eliminating the communication cost due to task migration upon one processor fails. The performance evaluation of the proposed method is carried out by incorporating it into a well known heuristic scheduling, and the experimental results fully demonstrate the usefulness of the proposed algorithm.