DocumentCode
3149219
Title
A Hiererachical, Error-Tolerant Compactor
Author
Kingsley, Christopher
Author_Institution
VLSI Technology, Inc., San Jose, CA
fYear
1984
fDate
25-27 June 1984
Firstpage
126
Lastpage
132
Abstract
This paper describes a compactor that is practical for compacting whole chips that are designed hierarchically, and can produce a reasonable result in spite of the layout being over-constrained. The layout produced is good enough to be used in high volume chips. The compactor is currently used in a cell layout system and a chip assembly tool.
Keywords
Assembly systems; Buildings; CMOS technology; Compaction; Connectors; Contacts; MOS devices; Tiles; Very large scale integration; Video recording;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1984. 21st Conference on
ISSN
0738-100X
Print_ISBN
0-8186-0542-1
Type
conf
DOI
10.1109/DAC.1984.1585785
Filename
1585785
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