• DocumentCode
    3149306
  • Title

    Magic´s Incremental Design-Rule Checker

  • Author

    Taylor, George S. ; Ousterhout, John K.

  • Author_Institution
    Computer Science Division, Electrical Engineering and Computer Sciences Department, University of California, Berkeley, CA
  • fYear
    1984
  • fDate
    25-27 June 1984
  • Firstpage
    160
  • Lastpage
    165
  • Abstract
    The Magic VLSI layout editor contains an incremental design-rule checker. When the circuit is changed, only the modified areas are rechecked. The checker runs continuously in background to keep information about design-rule violations up-to-date. This paper describes the basic rule checker, which operates on edges in the layout, and the techniques used to perform incremental checking on hierarchical designs.
  • Keywords
    design-rule checking; interactive layout editor; Circuits; Computer science; Data structures; Design automation; Displays; Geometry; MOS devices; Tiles; Velocity measurement; Very large scale integration; design-rule checking; interactive layout editor;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 1984. 21st Conference on
  • ISSN
    0738-100X
  • Print_ISBN
    0-8186-0542-1
  • Type

    conf

  • DOI
    10.1109/DAC.1984.1585790
  • Filename
    1585790
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3149306