• DocumentCode
    3149559
  • Title

    A Systolic Design Rule Checker

  • Author

    Kane, RaJiv ; Sahni, Sartaj

  • Author_Institution
    University of Minnesota
  • fYear
    1984
  • fDate
    25-27 June 1984
  • Firstpage
    243
  • Lastpage
    250
  • Abstract
    We develop a systolic design rule checker (SDRC) for rectilinear geometries. This SDRC reports all width and spacing violations. It is expected to result in a significant speed up of the design rule check phase of chip design.
  • Keywords
    Design Rule Checks; feature width; rectilinear geometries; spacing; systolic systems; Algorithm design and analysis; Chip scale packaging; Circuits; Complexity theory; Computer architecture; Design automation; Geometry; Logic; Routing; Wire; Design Rule Checks; feature width; rectilinear geometries; spacing; systolic systems;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 1984. 21st Conference on
  • ISSN
    0738-100X
  • Print_ISBN
    0-8186-0542-1
  • Type

    conf

  • DOI
    10.1109/DAC.1984.1585802
  • Filename
    1585802
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3149559