Title :
Matrix method for latch-up free demonstration in a triple-well bulk-silicon technology
Author_Institution :
Fraunhofer-Inst. fur Festkorpertechnol., Munchen, Germany
Abstract :
A CMOS inverter made in bulk silicon by triple-well technology is examined with respect to its latch-up behavior. With this exemplary circuit and a matrix like scheme it can be proved that the conditions for the occurrence of the latch-up effect are not met in any case. It is demonstrated for the first time that this type of technology leads to completely latch-up free CMOS circuits in bulk silicon and, therefore, extremely good hardness against transient radiation induced effects can be achieved without using SOI (Silicon On Insulator) and SOS (Silicon On Sapphire). Improved insensitivity to SEU (Single Event Upset) can be expected
Keywords :
CMOS integrated circuits; integrated circuit technology; integrated logic circuits; invertors; radiation hardening (electronics); CMOS circuits; CMOS inverter; SEU; hardness; latch-up behavior; latch-up free demonstration; transient radiation induced effects; triple-well bulk-silicon technology; CMOS technology; Circuits; Inverters; Paper technology; Power supplies; Silicon on insulator technology; Single event upset; Thyristors; Variable structure systems; Voltage;
Conference_Titel :
Radiation and its Effects on Devices and Systems, 1991. RADECS 91., First European Conference on
Conference_Location :
La Grande-Motte
Print_ISBN :
0-7803-0208-7
DOI :
10.1109/RADECS.1991.213619
