Title :
A 8 K×8 radiation hardened SRAM
Author_Institution :
MATRA MHS-La Chantrerie, Nantes
Abstract :
Describes a 64 K (8 K×8) radiation hardened SRAM and the process modifications which contribute to achieve a satisfactory immunity to worst case heavy ion environments. This 64 K SRAM incorporates polysilicon feedback resistors in the memory cell to provide SEU immunity. These resistors, obtained by selected polysilicon silicidation, allow an access time of 55 ns in some process and temperature worst case conditions. Besides, one can significantly reduce leakage current degradations due to total dose effects by removing or biasing `off´ the parasitic transistors which exist in addition to `real´ transistors. Circuit simulations indicate a total dose immunity of 100 krads (Si)
Keywords :
CMOS integrated circuits; SRAM chips; ion beam effects; radiation hardening (electronics); 100E3 rad; 55 ns; 64 kbit; SEU immunity; leakage current; memory cell; parasitic transistors; polysilicon feedback resistors; polysilicon silicidation; process modifications; radiation hardened SRAM; temperature worst case conditions; total dose immunity; worst case heavy ion environments; Circuits; Content addressable storage; MOS devices; MOSFETs; Polarization; Presence network agents; Radiation hardening; Random access memory; Tin; Variable structure systems;
Conference_Titel :
Radiation and its Effects on Devices and Systems, 1991. RADECS 91., First European Conference on
Conference_Location :
La Grande-Motte
Print_ISBN :
0-7803-0208-7
DOI :
10.1109/RADECS.1991.213620