Title :
A hardened technology on SOI for analog devices
Author :
Dupont-Nivet, E. ; Delagnes, E. ; Leray, J.L. ; Martin, J.L. ; Montaron, J. ; Blanc, J.P. ; Delevoye, E. ; Gauthier, J. ; de Pontcharra, J. ; Truche, R. ; Beuville, E. ; Dentan, M. ; Fourches, N.
Author_Institution :
CEA, Centre d´´Etudes de Bruyeres-Le-Chatel, France
Abstract :
Presents a hardened and mixed analog-digital technology under development. This technology now includes a PJFET with a quite good hardness, CMOS transistors with a potential multi-megarad hardness and first tests of bipolar transistors with a not yet optimized structure (structure of the JFET). All the results achieved so far, together with the optimizations under way will lead to an analog technology with a digital capability and a high level of hardness (neutron fluence, cumulated dose, immunity to upsets) to address the needs of military applications and electronics for the elementary particles physics detectors of the next generation colliders
Keywords :
CMOS integrated circuits; bipolar transistors; insulated gate field effect transistors; junction gate field effect transistors; military equipment; mixed analogue-digital integrated circuits; particle detectors; radiation hardening (electronics); semiconductor-insulator boundaries; CMOS transistors; PJFET; bipolar transistors; colliders; cumulated dose; elementary particles physics detectors; military applications; mixed analog-digital technology; neutron fluence; potential multi-megarad hardness; upset immunity; Analog-digital conversion; CMOS technology; Detectors; Electronic equipment testing; Elementary particles; Immunity testing; Large Hadron Collider; Neutrons; Physics; Transistors;
Conference_Titel :
Radiation and its Effects on Devices and Systems, 1991. RADECS 91., First European Conference on
Conference_Location :
La Grande-Motte
Print_ISBN :
0-7803-0208-7
DOI :
10.1109/RADECS.1991.213629
