Title :
Hierarchical resampling architecture for distributed particle filters
Author :
Zheng, Ning ; Pan, Yun ; Yan, Xiaolang ; Huan, Ruohong
Author_Institution :
Inst. of VLSI Design, Zhejiang Univ., Hangzhou, China
Abstract :
In this paper, a hierarchical resampling (HR) architecture has been presented for distributed particle filters (PFs). The proposed architectures decomposes the resampling step into two hierarchies, of which the first one, called intermediate resampling, is conducted consecutively among processing elements (PEs) the moment new particles and their weights are generated by each PE, and the second one, named unitary resampling, is performed sequentially after the whole intermediate resampling procedure and shared by all PEs. Compared with traditional distributed architectures, the HR architecture eliminates the particle redistribution step, and has such advantages as short execution time, high memory efficiency and well scalability.
Keywords :
particle filtering (numerical methods); signal sampling; distributed particle filter; hierarchical resampling architecture; intermediate resampling procedure; processing element; unitary resampling; Hardware; Indexes; Memory management; Particle filters; RNA; Scalability; Architecture; distributed particle filters; hierarchical resampling; high memory efficiency; latency;
Conference_Titel :
Acoustics, Speech and Signal Processing (ICASSP), 2012 IEEE International Conference on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4673-0045-2
Electronic_ISBN :
1520-6149
DOI :
10.1109/ICASSP.2012.6288191