DocumentCode
3151086
Title
Notice of Retraction
Design of the time driving and image signal processing for linear CCD based on FPGA
Author
Zhao Yuan
Author_Institution
Eng. Coll., Chinese Armed Police Force, Xi´an, China
fYear
2011
fDate
16-18 April 2011
Firstpage
3088
Lastpage
3090
Abstract
Notice of Retraction
After careful and considered review of the content of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE´s Publication Principles.
We hereby retract the content of this paper. Reasonable effort should be made to remove all past references to this paper.
The presenting author of this paper has the option to appeal this decision by contacting TPII@ieee.org.
A variety of driving pulse should be designed well in order that the linear CCD is working stable in image measuring, In this paper, in the base of analyzing the driving pulse and time sequence of TCD 1501D linear CCD, by analyzing the output image 0 signal of CCD, the paper gives out CDS circuit in and out of the CCD. At last, the required time sequence driving has been designed and the result has been simulated accurately by the use of development platform of Quartus II 7.2 combining with VHDL. The result of the simulation indicates that the driving circuit is characterized by simple framework, low power consumption, and strong anti-jamming ability, which meet the demand of miniaturization for the project.
After careful and considered review of the content of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE´s Publication Principles.
We hereby retract the content of this paper. Reasonable effort should be made to remove all past references to this paper.
The presenting author of this paper has the option to appeal this decision by contacting TPII@ieee.org.
A variety of driving pulse should be designed well in order that the linear CCD is working stable in image measuring, In this paper, in the base of analyzing the driving pulse and time sequence of TCD 1501D linear CCD, by analyzing the output image 0 signal of CCD, the paper gives out CDS circuit in and out of the CCD. At last, the required time sequence driving has been designed and the result has been simulated accurately by the use of development platform of Quartus II 7.2 combining with VHDL. The result of the simulation indicates that the driving circuit is characterized by simple framework, low power consumption, and strong anti-jamming ability, which meet the demand of miniaturization for the project.
Keywords
CCD image sensors; driver circuits; field programmable gate arrays; image sampling; CDS circuit; FPGA; Quartus II 7.2; TCD 1501D linear CCD; VHDL; antijamming ability; correlated double sampling; driving circuit; driving pulse; image measuring; image signal processing; output image signal analysis; power consumption; time sequence driving; Arrays; Charge coupled devices; Driver circuits; EPROM; Field programmable gate arrays; Force measurement; Time measurement; correlated double sampling (CDS); field programmable gate array (FPGA); linear CCD; time driving;
fLanguage
English
Publisher
ieee
Conference_Titel
Consumer Electronics, Communications and Networks (CECNet), 2011 International Conference on
Conference_Location
XianNing
Print_ISBN
978-1-61284-458-9
Type
conf
DOI
10.1109/CECNET.2011.5768372
Filename
5768372
Link To Document