DocumentCode
3151152
Title
A Method for IC Layout Verification
Author
Marvik, Ola A.
Author_Institution
Electronics Research Laboratory, University of Trondheim, Trondheim, Norway
fYear
1984
fDate
25-27 June 1984
Firstpage
708
Lastpage
709
Abstract
A method for MOS integrated circuit layout verification based on net list extraction and logic simulation is presented. The net list elements are on the gate level or higher, defined by the user. A self developed net list extractor, NETEX, is described. NETEX is interfaced to a commercially available layout system and logic simulator. Results show that this is a fast and reliable way of connectivity checking. Limitations and further improvements are discussed.
Keywords
Circuit simulation; Costs; Documentation; Graphics; Integrated circuit layout; Laboratories; Libraries; Logic design; MOS integrated circuits; Pins;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1984. 21st Conference on
ISSN
0738-100X
Print_ISBN
0-8186-0542-1
Type
conf
DOI
10.1109/DAC.1984.1585890
Filename
1585890
Link To Document