Clock-gating-aware low launch WSA test pattern generation for at-speed scan testing

Capture power management has become a necessity to avoid at-speed scan testing yield loss, especially for modern complex and low power designs. This paper proposes a test pattern generation methodology that utilizes the available clock-gating mechanism, a popular low power design technique, to reduce the launch cycle weighted switching activity (WSA) for at-speed scan testing. Compared to previous techniques that consider clock-gating, a significant launch cycle WSA reduction is achieved without severe test pattern inflation.